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Iyo Complex Programmable Logic Device (CPLD) ndeyekushandisa-chaiyo Yakabatanidzwa Yakabatanidzwa Circuit (ASIC) muLSI (Yakakura Scale Integrated Circuit) Yakabatanidzwa Circuit).Yakakodzera kudzora yakanyanya dhijitari system dhizaini, uye kunonoka kwayo kutonga kuri nyore.CPLD ndeimwe yemidziyo inokurumidza kukura mumasekete akabatanidzwa.
Zvikamu zveCPLD
CPLD chinhu chakaomesesa programmable logic mudziyo une hukuru hwakakura uye hwakaomarara chimiro, icho chiri cheiyo yakakura-akakura akabatanidzwa maseketi.

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Product Detail

Product Tags

Product Attributes

Pbfree Code	Ehe
Rohs Code	Ehe
Chikamu Hupenyu Cycle Code	Active
Ihs Manufacturer	Iyo kambani LATTICE SEMICONDUCTOR CORP
Chikamu Package Code	QFP
Tsanangudzo Yepakeji	LFQFP,
Pin Count	100
Svika Kodhi Yekutevedzera	zvinoenderana
ECCN Code	EAR99
HTS Code	8542.39.00.01
Samacsys Mugadziri	Lattice Semiconductor
Chimwe Chinhu	INOSHANDAWO PA3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PQFP-G100
JESD-609 Code	e3
Urefu	14 mm
Unyoro Sensitivity Level	3
Nhamba Yezvipikiso Zvakatsaurirwa
Nhamba yeI/O Mitsetse
Nhamba Yezvakaiswa	55
Nhamba Yezvinobuda	55
Nhamba Yezviteshi	100
Kushanda Temperature-Max	85 °C
Kushanda Tembiricha-Min
Sangano	0 DEDICATED INPUTS, 0 I/O
Output Function	MIXED
Package Body Material	PLASTIC/EPOXY
Package Code	LFQFP
Package Equivalence Code	TQFP100,.63SQ
Package Shape	SQUARE
Package Style	FLTPACK, YAkaderera Mbiri, PITCH YAKANAKA
Packing Method	TRAY
Peak Reflow Temperature (Cel)	260
Power Supplies	2.5/3.3 V
Programmable Logic Type	FLASH PLD
Propagation Kunonoka	7.36 ns
Qualification Status	Not Qualified
Akagara Height-Max	1.6 mm
Supply Voltage-Max	3.462 V
Supply Voltage-Min	2.375 V
Supply Voltage-Nom	2.5 V
Surface Mount	EHE
Tembiricha Grade	ZVIMWE
Terminal Finish	Matte Tin (Sn)
Terminal Form	GULL BApiro
Terminal Pitch	0.5 mm
Terminal Position	QUAD
Nguva@Peak Reflow Temperature-Max (s)	30
Upamhi	14 mm

Product Sumo

Zvikamu zveCPLD

CPLD chinhu chakaomesesa programmable logic mudziyo une hukuru hukuru uye hwakaomesesa chimiro, icho chiri chemhando yehukuru-hukuru.masekete akabatanidzwa.

CPLD ine zvikamu zvishanu zvikuru: logical array block, macro unit, yakawedzerwa chigadzirwa nguva, programmable wired array uye I/O control block.

1. Logical Array Block (LAB)

Iyo inonzwisisika array block ine akatevedzana gumi nematanhatu maseru maseru, uye akawanda LABS akabatanidzwa pamwechete ne programmable array (PIA) uye bhazi repasi rose.

2. Macro unit

Iyo macro unit muMAX7000 nhevedzano ine matatu anoshanda mabhuroko: inonzwisisika array, chigadzirwa chekusarudza matrix, uye rejista inorongwa.

3. Yakawedzerwa nguva yechigadzirwa

Chigadzirwa chimwe chete chesero macro cell chinogona kudzoserwa kumashure kune inonzwisisika array.

4. Programmable wired array PIA

Imwe neimwe LAB inogona kubatana kuti iite inodiwa logic kuburikidza ne programmable wired array.Iri bhazi repasi rose inzira inogoneka inogona kubatanidza chero chiratidzo chechiratidzo mumudziyo kune kwainoenda.

5. I / O control block

Iyo I / O control block inobvumira yega I / O pini kuti igadziriswe yega yega yekupinza / kubuda uye bidirectional mashandiro.

Kuenzanisa kweCPLD uye FPGA

Kunyangwe zvese zviri zviviriFPGAuyeCPLDzvigadziriso zveASIC zvishandiso uye zvine akawanda akajairika maitiro, nekuda kwekusiyana kwechimiro cheCPLD neFPGA, ivo vane hunhu hwavo:

1.CPLD inonyanya kukodzera kuzadzisa maalgorithms akasiyana-siyana uye combinatorial logic, uye FP GA inonyanya kukodzera kupedzisa sequential logic.Mune mamwe mazwi, FPGA inonyanya kukodzera flip-flop yakapfuma chimiro, nepo CPLD inonyanya kukodzera flip-flop yakaganhurwa uye chigadzirwa term rakapfuma chimiro.

2.Kuenderera mberi kwemaitiro eCPLD anoona kuti kunonoka kwayo nguva kwakafanana uye kunofanotaurwa, asi iyo yakakamurwa nzira yeFPGA inogadzirisa kunonoka kwayo kusingatarisirwi.

3.FPGA ine zvakawanda zvinoshanduka kupfuura CPLD mukuronga.CPLD inorongedzerwa nekugadzirisa iyo logic basa neyakagadziriswa yemukati yekubatanidza wedunhu, nepo FPGA inorongwa nekuchinja wiring yemukati yekubatanidza.FP GA inogona kurongwa pasi pegedhi rine musoro, ukuwo CPLD yakarongwa pasi pechivharo chine musoro.

4.Kubatanidzwa kweFPGA kwakakwirira kudarika kweCPLD, uye ine yakanyanya kuoma wiring structure uye logic kushandiswa.

5.CPLD iri nyore kushandisa kupfuura FPGA.CPLD hurongwa uchishandisa E2PROM kana FASTFLASH tekinoroji, hapana chekunze ndangariro chip, iri nyore kushandisa.Nekudaro, iyo programming information yeFPGA inoda kuchengetwa mundangariro dzekunze, uye nzira yekushandisa yakaoma.

6. CPLDS inokurumidza kupfuura FPgas uye ine nguva yakawanda yekufungidzira.Izvi zvinodaro nekuti FPGas isuwo-level programming uye yakagovaniswa yekubatanidza inogamuchirwa pakati peCLBS, nepo CPLDS iri logic block-level programming uye mabatiro ari pakati pemabhuroki avo epfungwa akadzimwa.

7. Munzira yekuronga, CPLD inonyanya kuenderana neE2PROM kana FLASH memory programming, nguva dzehurongwa dzinosvika zviuru gumi, chakanakira ndechekuti iyo system inodzima ruzivo rwechirongwa haina kurasika.CPLD inogona kukamurwa kuita mapoka maviri: programming pane programmer uye programming pane system.Yakawanda yeFPGA yakavakirwa paSRAM programming, ruzivo rwehurongwa rwunorasika kana sisitimu yadzimwa, uye data rehurongwa rinoda kunyorwa kuSRAM kubva kunze kwechishandiso pese painobatidzwa.Kubatsira kwayo ndekwekuti inogona kurongwa chero nguva, uye inogona kurongwa nekukurumidza mubasa, kuitira kuti iwane simba rekugadzirisa padanho rebhodhi uye system level.

8. Kuvanzika kweCPLD kwakanaka, kuvanzika kweFPGA hakuna kunaka.

9.Muzhinji, simba rekushandisa reCPLD rakakura kudarika reFPGA, uye yakakwirira yedhigirii yekubatanidza, inonyanya kuoneka.

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