XC2C256-7TQG144C QFP144 xilinx chips 1.8V Input-output yakawanda 118 FLASH PLD IC zvemagetsi

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 Iyo yakaoma programmable logic mudziyo (CPLD) chishandiso chine musoro chine hurongwa hwakazara UYE/KANA arrays uye macrocell.Macrocells ndiwo matombo makuru ekuvaka eCPLD, ane maitiro akaomarara ekuita uye pfungwa yekushandisa disjunctive yakajairika fomu mataurirwo.UYE/OR arrays anonyatso kurongeka uye ane mutoro wekuita akasiyana logic mabasa.Macrocells anogona zvakare kutsanangurwa seanoshanda mabhuraki ane basa rekuita sequential kana combinatorial logic.

 Iyo yakaoma programmable logic mudziyo chigadzirwa chine hunyanzvi chichienzaniswa neyekare logic zvishandiso se programmable logic arrays (PLAs) uye Programmable Array Logic (PAL).Iwo ekutanga logic zvishandiso akange asina kurongeka, saka pfungwa yacho yakavakwa nekubatanidza akawanda logic machipi pamwechete.A CPLD ine kuomarara pakati pePAL uye munda-inorongwa gedhi arrays (FPGAs).Iyo zvakare ine zvimiro zvekuvaka zveese maPAL uye maFPGAs.Musiyano mukuru wekuvaka pakati peCPLD neFPGA ndewekuti maFPGA akavakirwa pamatafura ekutarisa, nepo CPLDs yakavakirwa pagungwa-remagedhi.

Izvo zvakajairika maficha eCPLDs uye FPGAs ndezvekuti iwo ese ane hukuru hukuru hwemagedhi uye inochinjika gadziriro yepfungwa.Ipo zvakajairika maficha pakati peCPLDs nePALs anosanganisira isiri-inotenderera yekumisikidza ndangariro.CPLDs vatungamiriri mumusika wezvinorongwa logic madivayiri, ane akawanda mabhenefiti senge advanced programming, mutengo wakaderera, kusaita-kusagadzikana uye nyore kushandisa.

 Ayakaoma programmable logic device(CPLD) ndiye aprogrammable logic devicenekuoma kunzwisisa pakati peiyo yePALsuyeFPGAs, uye zvimiro zvezvivakwa zvezvose.Iyo huru yekuvaka yeCPLD ndeyemacrocell, iyo ine logic kushandisadisjunctive normal formmatauriro uye mamwe hunyanzvi logic mashandiro.

Features[edit]

Mamwe maficha eCPLD akafanana nePALs:

• Non-volatile configuration memory.Kusiyana neFPGA dzakawanda, gadziriro yekunzeROMhaidiwi, uye CPLD inogona kushanda nekukasira pakutanga system-up.
• Kune akawanda enhaka CPLD zvishandiso, nzira inomanikidza akawanda logic mabhuroko kuti ave nekuisa uye kubuda masiginecha akabatana nemapini ekunze, kuderedza mikana yekuchengetedza yemukati yenyika uye yakadzika akaturikidzana pfungwa.Izvi kazhinji hazvisi chinhu kune yakakura CPLDs uye itsva CPLD chigadzirwa mhuri.

Zvimwe zvinhu zvakafanana nazvoFPGAs:

• Nhamba huru yemagedhi aripo.CPLDs kazhinji ine yakaenzana nezviuru kusvika makumi ezviuru zvemagedhi anonzwisisika, kubvumira kushandiswa kwezvine mwero zvakaoma data kugadzirisa michina.PALs kazhinji ane mazana mashoma emagedhi akaenzana zvakanyanya, nepo maFPGAs achiwanzo siyana kubva kumakumi ezviuru kusvika kumamiriyoni akati wandei.
• Zvimwe zvinopihwa zvepfungwa zvinochinjika kupfuurasum-of-chigadzirwamatauriro, anosanganisira nzira dzakaomesesa dzemhinduro pakati pema macro masero, uye hunyanzvi hwekuita mabasa akasiyana siyana anowanzo shandiswa, senge.integer arithmetic.

Musiyano unonyanya kuoneka pakati peCPLD hombe neFPGA diki kuvepo kwe-on-chip isiri-volatile memory muCPLD, iyo inobvumira CPLDs kushandiswa "boot loader” mabasa, usati wapa kutonga kune mamwe maturusi asina yavo yekugara chirongwa chekuchengetedza.Muenzaniso wakanaka ndewekuti CPLD inoshandiswa kurodha dhizaini yekumisikidza yeFPGA kubva kune isiri-inotenderera ndangariro.^[1]

Misiyano[edit]

CPLDs yaive nhanho yekushanduka kubva kune zvidiki zvishandiso zvakavatangira,PLAs(kutanga kutumirwa neSignetics), uyePALs.Avawo ndivo vakatangirwastandard logiczvigadzirwa, izvo zvaisapa kurongeka uye zvakashandiswa kuvaka logic mabasa nekuita wiring akati wandei akajairwa logic chips (kana mazana azvo) pamwe chete (kazhinji newaya pane yakadhindwa redunhu bhodhi kana mabhodhi, asi dzimwe nguva, kunyanya kune prototyping, uchishandisa.waya kuputirawiring).

Musiyano mukuru pakati peFPGA uye CPLD mudziyo zvivakwa ndezvekuti maCPLDs ari mukati akavakirwamatafura ekutarisa(LUTs) nepo FPGAs dzichishandisalogic blocks.